A ten-dollar laser can now destroy a forty-thousand-dollar GPU. That single fact exposes the flaw in the industry's favorite story about photonics. Copper interconnects have hit a physical breaking point that trillion-parameter models cannot engineer around1. Silicon photonics is the crowned solution. But the coronation is premature.
The dominant narrative treats optical I/O as a frictionless silver bullet: swap copper for light to escape the power crisis and scale GPUs. That framing is wrong in a specific and expensive way. Photonics does not eliminate the AI scaling constraint. It relocates it.
Optics doesn't break the ceiling on AI scaling. It picks the ceiling up and moves it from the data-center power grid onto TSMC's packaging lines and a handful of Indium Phosphide fabs.
Solving a visible constraint like interconnect power silently manufactures three new ones: packaging capacity, laser supply, and asymmetric failure risk. I call this the second-order bottleneck. Every player racing toward co-packaged optics is walking into a set of chokepoints that mainstream coverage ignores. I map all three below, along with the strategic inversion they set up.
Why Copper Hit a Wall and Optics Only Moved It
The Copper Wall is the point where signal loss and power draw of electrical wiring become the dominant constraint on the entire system2. Next-generation XPUs demand bandwidths climbing toward 28.8 Tbps. At that figure, traditional copper interconnects and electrical SerDes architectures become mathematically unviable on power alone3.
Optics answers this cleanly on the physics. Ayar Labs' TeraPHY chiplet delivers up to 5x to 10x higher bandwidth. It also provides 10x lower latency and 4x to 8x better power efficiency than pluggable optics plus electrical SerDes4. Lightmatter's Nick Harris frames the shift bluntly. Photonics' moment arrived not because it suddenly got better, but because copper reached its limit5. On that narrow question, the industry is right.
The error is treating a bandwidth solution as a scaling solution. Compute stopped being the primary bottleneck a while ago. The constraint moved to I/O. Optics addresses I/O. What it ignores is that building optical interconnect at scale demands the exact same scarce industrial inputs as building the GPU it connects. You do not escape a bottleneck by shifting load onto an input that is already constrained. You just make the constraint harder to see.
Packaging Cannibalization: Optical Engines Fight GPUs for the Same Foundry Lines
Co-packaged optics requires advanced packaging, specifically the CoWoS and SoIC processes that already sit at the center of AI compute. TSMC's COUPE platform uses SoIC-X chip stacking to place an electrical die directly on top of a photonic die, achieving ultra-low impedance and superior energy efficiency versus conventional stacking6. That is genuinely a better mousetrap. It also consumes the exact packaging capacity that HBM stacks and AI accelerators are fighting over right now.
I call this Packaging Cannibalization. Every wafer of advanced-packaging capacity spent building the optical interconnect is a wafer not spent building the accelerator it serves. CoWoS-S already integrates high-bandwidth memory to logic in a 2.5D silicon interposer7. When optical engines join that queue, they do not get a separate factory. They enter the existing queue, fighting AI accelerators for TSMC's limited tool time. The second-order effect is a supply squeeze that compounds. More AI demand drives more optical interconnect, which consumes more of the capacity that AI accelerators need, tightening the very bottleneck optics was supposed to relieve.
TSMC understands its pricing power here perfectly. COUPE is positioned to occupy the same role in silicon photonics that CoWoS occupies in AI packaging: a foundry-and-packaging platform, not a merchant switch product8. The roadmap extends to panel-level CoPoS by 2029, framed explicitly as the successor to CoWoS9. Samsung, sensing a second monopoly forming, released its own silicon photonics foundry roadmap at OFC 2026 to apply competitive pressure10.
| Chokepoint | What it constrains | Who controls it |
|---|---|---|
| Advanced packaging (CoWoS/SoIC) | Both GPUs and optical engines | TSMC (COUPE), Samsung challenging |
| Indium Phosphide lasers | Light generation for all optics | InP fabs, Veeco tooling |
| ELSFP / modular design | Failure isolation and uptime | System architects (NVIDIA et al.) |
Silicon Cannot Lase, So Indium Phosphide Becomes the Hidden Chokepoint
Silicon is superb at computation and terrible at generating light. Every high-performance optical transceiver, no matter how advanced its packaging, still depends on Indium Phosphide lasers and photodetectors11. That material dependency sits entirely outside the traditional silicon supply chain. It is nowhere near ready for the volume AI is about to demand.
The evidence is in the capital. Veeco announced more than $250 million in equipment orders specifically to manufacture InP lasers, with deliveries starting in 2026 and accelerating sharply in 202712. Orders of that size signal that current InP capacity is inadequate for what is coming. Aeluma put it plainly. The AI data-center buildout is outpacing the photonics supply chain, and customers are evaluating quantum-dot laser technology purely to bridge near-term supply gaps13.
Read the timeline against the roadmaps and the mismatch jumps out. COUPE targets volume production in 2026. The InP laser capacity to feed it does not significantly accelerate until 2027. The packaging platform arrives before its critical input does.
Optical Blast Radius: When a Cheap Laser Bricks an Expensive GPU
Integration has a dark side the efficiency numbers hide. When you weld the light source onto the compute package, you fuse their fates. A single laser failure in a poorly designed CPO architecture can render a $40,000 GPU or a $200,000 switch unusable, because you cannot replace the failed component without discarding the whole assembly14. I call this the Optical Blast Radius. It measures the total dollar value destroyed when the cheapest component in an integrated optical package fails.
The physics makes this worse. Repeated thermal cycling in densely integrated data-center optics degrades laser lifetime rapidly, precisely the failure mode most likely to trigger in a hot, always-on AI cluster15. You are attaching the least durable element to the most expensive one, inside the harshest thermal environment in the building.
"The key challenges for CPO are optical fiber alignment, packaging yield and whether systems can continue operating without interruption when components need replacement." Kim Jung-ho, The Elec
The industry's response reveals the real design constraint. The architecture gaining mainstream traction is ELSFP (External Laser Source Form factor Pluggable), which physically separates the laser and mounts it as a replaceable external module on the front of the switch14. NVIDIA's CPO approach does the same, using external light sources specifically to avoid the reliability trap where thermal cycling forces costly network interruptions16. The lesson is counterintuitive. The winning optical design is the one that keeps the light source out of the package. Maximum integration is not the goal. Minimizing the blast radius is.
Fabric Value Inversion: How Optics Threatens to Commoditize the GPU
The deepest consequence is strategic, not physical. Perfect optical interconnect makes memory pooling and low-latency fabric across a cluster genuinely viable. That quietly undermines the case for the monolithic, do-everything accelerator. Celestial AI's Photonic Fabric is designed exactly for high-bandwidth, low-latency connectivity across large-scale deployments17. It is the kind of fabric that lets many cheaper components behave like one giant machine.
If the fabric becomes good enough, value migrates from the compute node to the optical switching layer that binds nodes together. The GPU risks becoming the commodity. The fabric becomes the moat. The money is already moving to front-run it. Marvell's acquisition of Celestial AI folds Photonic Fabric into a networking incumbent's portfolio18, a bet that whoever owns the fabric owns the value. The broader consolidation, alongside the industry pivot from component-level pluggable transceivers to platform-level foundry-integrated optical engines19, tells you where incumbents think the profit pool is heading.
NVIDIA's and TSMC's maneuvers look different in this light. Locking up laser capacity and packaging lines is not only about scaling faster. It is a defensive veto. Control the inputs to the fabric, and you control whether anyone can commoditize your compute with it.
What Founders and Architects Should Do Before 2027
Treat the second-order bottleneck as your planning baseline, not an edge case. If your roadmap assumes optics arrives frictionless in 2026, it is mispriced. Broadcom is pushing VCSEL-based Near-Package Optics as a bridge to scale AI clusters before full CPO matures3. That phasing is a signal to design for a staged transition rather than a clean cutover.
- Architect for the Optical Blast Radius from day one. Favor ELSFP-style separation so a cheap failure never strands expensive silicon.
- Model your exposure to two chokepoints you do not control: InP laser supply and TSMC/Samsung packaging allocation. Secure position early rather than assuming spot availability.
- Watch the Fabric Value Inversion if you build accelerators. The fabric layer is where margin is migrating, and yield hurdles in fiber alignment and packaging are what will gate the timeline.
The companies that win the next cluster generation will not be the ones with the best photonics. Hardware buyers who fail to secure InP laser supply by Q3 2026 will find their $40,000 GPUs sitting idle in warehouses, waiting on a $10 part that simply does not exist.
The key challenges for CPO are optical fiber alignment, packaging yield and whether systems can continue operating without interruption when components need replacement.
